Digital circuits and microprocessors

What to remember

• NAND and NOR are universal gates; any Boolean function can be built from either one alone.
• Combinational circuits depend only on present inputs; sequential circuits also depend on stored past state (flip-flops with a clock).
• The 8085 is an 8-bit microprocessor with a 16-bit address bus, so it can address 64 KB of memory; its data bus is 8 bits and multiplexed with the lower address byte.

Number systems and codes

Binary uses base 2, octal base 8, hexadecimal base 16. To convert binary to hexadecimal, group the bits in fours from the right. Example: 1011 0110₂ = B6₁₆ = 182₁₀. To convert decimal to binary, divide repeatedly by 2.

Negative numbers use 2's complement: invert all bits and add 1. For n bits, the range is −2^(n−1) to +2^(n−1) − 1. For 8 bits, this is −128 to +127. Example: −5 in 8-bit 2's complement is 1111 1011.

Codes: BCD stores each decimal digit in 4 bits (digits 0-9). Gray code changes only one bit between successive numbers, which avoids errors in position encoders. Excess-3 is a self-complementing code. ASCII is a 7-bit character code. A parity bit detects a single-bit error.

Boolean algebra and gates

Basic laws: A + A' = 1; A·A' = 0; A + AB = A; A + A'B = A + B. De Morgan's laws: (A·B)' = A' + B' and (A + B)' = A'·B'.

Simplification uses Karnaugh maps (K-map). Group 1s in blocks of 1, 2, 4, 8 (powers of 2); larger groups give simpler terms. Don't-care conditions can be used as 1 or 0 to make bigger groups. A Boolean expression with n variables has 2^n minterms.

Combinational circuits

Half adder: Sum = A ⊕ B, Carry = A·B. Full adder: Sum = A ⊕ B ⊕ Cin, Carry = AB + Cin(A ⊕ B). A full adder can be built from two half adders and an OR gate. A ripple-carry adder is slow because carry travels through every stage; a carry-look-ahead adder is faster.

A multiplexer (MUX) selects one of 2^n inputs using n select lines. A 4:1 MUX needs 2 select lines. A demultiplexer does the reverse. A decoder with n inputs gives 2^n outputs (3-to-8 decoder). An encoder gives a binary code for the active input. A comparator compares two binary numbers. Any n-variable function can be implemented by a 2^n:1 MUX, or by a 2^(n−1):1 MUX with one variable used as data.

Sequential circuits

A JK flip-flop with J=K=1 and a clock of frequency f gives an output of f/2. The race-around condition occurs in a level-triggered JK flip-flop when the clock pulse is longer than the propagation delay; it is cured by master-slave or edge-triggered design. Characteristic equations: D: Q⁺ = D; T: Q⁺ = T ⊕ Q; JK: Q⁺ = JQ' + K'Q.

Counters: an n-bit ripple (asynchronous) counter has 2^n states (modulus 2^n); an n-flip-flop counter divides frequency by 2^n. A mod-N counter needs the smallest n with 2^n ≥ N. Synchronous counters clock all flip-flops together and are faster. A decade counter is mod-10 and uses 4 flip-flops. A ring counter with n flip-flops has n states; a Johnson (twisted-ring) counter has 2n states. Registers: SISO, SIPO, PISO, PIPO shift registers store and shift data.

Memory: ROM is non-volatile; PROM, EPROM (UV erasable), EEPROM (electrically erasable), flash. RAM is volatile: SRAM (flip-flop cells, fast, no refresh) and DRAM (capacitor cells, needs refresh). A memory with n address lines has 2^n locations; capacity = 2^n × word length.

Logic families

Fan-out is the number of gates one output can drive. Noise margin = difference between the output and input logic levels. Propagation delay limits speed. Data converters: an n-bit DAC has 2^n levels; step size = full-scale/(2^n − 1) in the common definition. A flash ADC is fastest; a successive-approximation ADC is a common medium-speed type; a dual-slope ADC is accurate and slow.

The 8085 microprocessor

Features: 8-bit data, 16-bit address, +5 V supply, 3 MHz typical clock, 40-pin package, on-chip clock generator. AD0-AD7 carry the lower address byte and data (multiplexed); ALE (address latch enable) goes high at the start of a machine cycle so that an external latch can hold the lower address byte. A15-A8 carry the upper address byte.

Registers: accumulator A, flag register, B, C, D, E, H, L (8-bit; used in pairs BC, DE, HL), stack pointer SP and program counter PC (16-bit). The flags are Sign, Zero, Auxiliary Carry, Parity and Carry. The HL pair acts as memory pointer M.

Control signals: RD', WR', IO/M' (high for I/O, low for memory), S0 and S1. Interrupts: TRAP (highest priority, non-maskable, edge and level sensitive), RST 7.5, RST 6.5, RST 5.5, INTR (lowest priority). Vector addresses: TRAP 0024H, RST 5.5 002CH, RST 6.5 0034H, RST 7.5 003CH.

Instruction examples: MOV A,B copies B to A. MVI A,32H loads an immediate byte. LDA 2050H loads A from memory. STA stores A. ADD B adds B to A. INR increments. CALL pushes the return address on the stack. PUSH and POP use the stack, which grows downward. Instruction lengths are 1, 2 or 3 bytes. Addressing modes: immediate, register, direct, register-indirect, implied. Machine cycles include opcode fetch (4 T-states in the 8085, the longest of the common cycles), memory read or write (3 T-states) and I/O cycles. Time of one T-state = 1/clock frequency; with a 3 MHz clock, 1 T = 0.333 µs.

Peripherals: 8255 gives 24 I/O lines in three ports (A, B, C). 8253/8254 is a programmable timer; 8259 is an interrupt controller; 8237 is a DMA controller. The 8086 is a 16-bit processor with a 20-bit address bus (1 MB).

Canonical forms, hazards and timing

A sum of products (SOP) lists the minterms where the function is 1; a product of sums (POS) lists the maxterms where it is 0. A minterm of n variables has every variable once, in true or complemented form. The number of different Boolean functions of n variables is 2^(2^n); for 2 variables it is 16. A static hazard is a momentary glitch in the output when one input changes; it can be removed by adding a redundant term in the K-map. Setup time is the time data must be stable before the clock edge; hold time is the time it must stay stable after the edge. The maximum clock frequency of a synchronous circuit is set by flip-flop delay plus logic delay plus setup time.

Programmable logic and interfacing

A PLA has a programmable AND array and a programmable OR array. A PAL has a programmable AND array and a fixed OR array. A ROM is a fixed AND array (decoder) with a programmable OR array. A CPLD and an FPGA are larger programmable devices; an FPGA is built from look-up tables (LUTs) and flip-flops. Tri-state buffers allow many devices to share one bus; only one device may drive the bus at a time. A decoder is used for memory address decoding: higher address lines choose the chip, lower lines choose the location inside the chip. Memory-mapped I/O treats ports as memory locations and uses memory instructions; I/O-mapped I/O uses separate IN and OUT instructions and the IO/M' signal. Data transfer methods are programmed I/O (polling), interrupt-driven I/O and DMA. DMA is fastest for large blocks because the processor is not involved in each byte.

Worked examples

• 1. A memory with 12 address lines and 8-bit words holds 4096 × 8 bits = 4 KB.
• 2. A mod-60 counter needs 6 flip-flops, since 2⁶ = 64 ≥ 60.
• 3. A 4-bit ripple counter driven by 16 kHz output on its last stage: 16 kHz/16 = 1 kHz.
• 4. 8085 at 3 MHz, instruction with 7 T-states: 7 × 0.333 = 2.33 µs.

Exam traps

• NAND/NOR are universal; AND/OR/XOR are not.
• Johnson counter gives 2n states; ring counter gives n.
• JK with J=K=1 toggles; SR with S=R=1 is forbidden.
• The 8085 has a 16-bit address bus but 8-bit data bus.
• ALE is used to demultiplex AD0-AD7.
• TRAP is non-maskable; INTR has the lowest priority.
• SRAM does not need refresh; DRAM does.
• Gray code changes one bit at a time; BCD does not.

One-liners

• 1. 2's complement = invert and add 1.
• 2. A full adder has 3 inputs and 2 outputs.
• 3. A 3-to-8 decoder has 3 inputs and 8 outputs.
• 4. 4:1 MUX has 2 select lines.
• 5. T flip-flop with T=1 divides clock by 2.
• 6. n flip-flops give mod 2^n in a ripple counter.
• 7. EPROM is erased by ultraviolet light.
• 8. CMOS has the lowest static power consumption.
• 9. 8085 can address 64 KB.
• 10. Flash ADC is the fastest ADC type.
• 11. The 8085 flags are S, Z, AC, P and CY.
• 12. 8255 has three 8-bit ports.

Practice questions

1. Which gate is called a universal gate?

   1. XNOR
   2. XOR
   3. AND
   4. NAND
   Answer

   D. NAND

   NAND (and NOR) can realise every Boolean function.

2. The binary number 1011 0110 in hexadecimal is

   1. D6
   2. B6
   3. 6B
   4. B3
   Answer

   B. B6

   1011 = B, 0110 = 6.

3. The 8-bit 2's complement representation of −5 is

   1. 11111010
   2. 10000101
   3. 00000101
   4. 11111011
   Answer

   D. 11111011

   +5 = 00000101; invert = 11111010; add 1 = 11111011.

4. The range of an 8-bit signed number in 2's complement is

   1. 0 to 255
   2. −127 to +127
   3. −128 to +127
   4. −256 to +255
   Answer

   C. −128 to +127

   −2^7 to 2^7 − 1.

5. Which code changes only one bit between successive numbers?

   1. Gray code
   2. ASCII
   3. Excess-3
   4. BCD
   Answer

   A. Gray code

   Gray code is a unit-distance code.

6. The expression A + A'B simplifies to

   1. B
   2. A + B
   3. A·B
   4. A
   Answer

   B. A + B

   Absorption-type identity: A + A'B = A + B.

7. According to De Morgan's law, (A + B)' equals

   1. A + B'
   2. A·B
   3. A'·B'
   4. A' + B'
   Answer

   C. A'·B'

   The complement of an OR is the AND of complements.

8. The carry output of a full adder is

   1. A ⊕ B ⊕ Cin
   2. A·B·Cin
   3. A + B + Cin
   4. AB + Cin(A ⊕ B)
   Answer

   D. AB + Cin(A ⊕ B)

   Carry = AB + Cin(A⊕B); the sum is the 3-way XOR.

9. How many select lines does a 16:1 multiplexer need?

   1. 2
   2. 8
   3. 4
   4. 16
   Answer

   C. 4

   2^4 = 16.

10. A 3-to-8 decoder has how many output lines?

    1. 8
    2. 3
    3. 6
    4. 16
    Answer

    A. 8

    n inputs give 2^n outputs.

11. A 4:1 multiplexer can implement any function of how many variables using only the multiplexer, if one variable is given as data input?

    1. 2 variables only
    2. 4 variables with no extra gates
    3. 5 variables
    4. 3 variables
    Answer

    D. 3 variables

    2 select lines + 1 variable fed to data lines = 3 variables.

12. In a JK flip-flop, J = K = 1 causes the output to

    1. set to 1
    2. toggle at each clock
    3. reset to 0
    4. hold its value
    Answer

    B. toggle at each clock

    Toggle mode.

13. The forbidden input condition of an SR flip-flop is

    1. S = 0, R = 1
    2. S = R = 1
    3. S = 1, R = 0
    4. S = R = 0
    Answer

    B. S = R = 1

    S = R = 1 gives an undefined next state.

14. Race-around condition occurs in

    1. level-triggered JK flip-flop with J = K = 1
    2. edge-triggered D flip-flop
    3. master-slave JK flip-flop
    4. T flip-flop with T = 0
    Answer

    A. level-triggered JK flip-flop with J = K = 1

    Output toggles repeatedly if the pulse is longer than the propagation delay.

15. The number of flip-flops needed for a mod-60 counter is

    1. 6
    2. 7
    3. 5
    4. 60
    Answer

    A. 6

    2^6 = 64 ≥ 60 but 2^5 = 32 < 60.

16. A 4-bit ripple counter is clocked at 32 kHz. The output frequency of the last flip-flop is

    1. 16 kHz
    2. 2 kHz
    3. 8 kHz
    4. 4 kHz
    Answer

    B. 2 kHz

    32/16 = 2 kHz.

17. A Johnson counter with 5 flip-flops has how many distinct states?

    1. 25
    2. 5
    3. 10
    4. 32
    Answer

    C. 10

    Johnson counter has 2n states.

18. A ring counter with 4 flip-flops has how many states?

    1. 8
    2. 4
    3. 16
    4. 2
    Answer

    B. 4

    Ring counter has n states.

19. A memory chip has 12 address lines and 8 data lines. Its capacity is

    1. 12 KB
    2. 1 KB
    3. 8 KB
    4. 4 KB
    Answer

    D. 4 KB

    2^12 × 8 bits = 4096 bytes.

20. Which memory type is volatile?

    1. SRAM
    2. Mask ROM
    3. EEPROM
    4. EPROM
    Answer

    A. SRAM

    RAM loses data when power is removed.

21. Dynamic RAM needs periodic refresh because it stores data in

    1. fuses
    2. magnetic cores
    3. flip-flops
    4. capacitors
    Answer

    D. capacitors

    Charge on a capacitor leaks away.

22. EPROM is erased by exposure to

    1. ultraviolet light
    2. a high-voltage pulse only
    3. magnetic field
    4. infra-red light
    Answer

    A. ultraviolet light

    EPROM has a quartz window for UV erase.

23. Which logic family has the lowest static power dissipation?

    1. DTL
    2. TTL
    3. CMOS
    4. ECL
    Answer

    C. CMOS

    CMOS draws current mainly during switching.

24. The fastest type of ADC is the

    1. counter-type ADC
    2. flash ADC
    3. successive-approximation ADC
    4. dual-slope ADC
    Answer

    B. flash ADC

    Flash uses parallel comparators, converting in one step.

25. An 8-bit DAC has how many distinct output levels?

    1. 8
    2. 512
    3. 255
    4. 256
    Answer

    D. 256

    2^8 = 256.

26. The number of address lines of the 8085 microprocessor is

    1. 20
    2. 32
    3. 16
    4. 8
    Answer

    C. 16

    16 address lines give 64 KB.

27. The 8085 lower address byte is separated from data using the signal

    1. RD'
    2. ALE
    3. WR'
    4. IO/M'
    Answer

    B. ALE

    ALE tells an external latch to hold AD0-AD7 as the address.

28. The highest-priority interrupt of the 8085 is

    1. INTR
    2. RST 5.5
    3. RST 7.5
    4. TRAP
    Answer

    D. TRAP

    TRAP is non-maskable and has the top priority.

29. The vector address of RST 7.5 in the 8085 is

    1. 003CH
    2. 0034H
    3. 0024H
    4. 002CH
    Answer

    A. 003CH

    RST 5.5 = 2C, 6.5 = 34, 7.5 = 3C.

30. How many flags are there in the 8085 flag register?

    1. 8
    2. 5
    3. 4
    4. 3
    Answer

    B. 5

    Sign, Zero, Auxiliary Carry, Parity, Carry.

31. An 8085 runs at 3 MHz. An instruction needs 6 T-states. Its execution time is

    1. 6 µs
    2. 0.5 µs
    3. 2 µs
    4. 18 µs
    Answer

    C. 2 µs

    T = 1/3 µs; 6 × 1/3 = 2 µs.

32. In the 8085, the pair of registers commonly used as a memory pointer is

    1. BC
    2. DE
    3. HL
    4. SP only
    Answer

    C. HL

    HL forms the memory pseudo-register M.

33. The stack in the 8085 grows toward

    1. the I/O ports
    2. the ROM area
    3. higher memory addresses
    4. lower memory addresses
    Answer

    D. lower memory addresses

    SP decreases on PUSH.

34. The Intel 8255 provides how many I/O lines?

    1. 24
    2. 16
    3. 8
    4. 32
    Answer

    A. 24

    Three 8-bit ports A, B and C.

35. Total addressable memory of the 8086 is

    1. 1 MB
    2. 4 MB
    3. 64 KB
    4. 16 MB
    Answer

    A. 1 MB

    20 address lines: 2^20 bytes.

36. Consider the statements. 1. NOR gate is a universal gate. 2. XOR gate is a universal gate. Which is/are correct?

    1. 1 only
    2. 2 only
    3. Both 1 and 2
    4. Neither 1 nor 2
    Answer

    A. 1 only

    NOR is universal; XOR alone is not.

37. Consider the statements. 1. A Gray code changes one bit at a time. 2. BCD represents each decimal digit using 4 bits. Which is/are correct?

    1. 1 only
    2. 2 only
    3. Both 1 and 2
    4. Neither 1 nor 2
    Answer

    C. Both 1 and 2

    Both statements are standard properties.

38. Consider the statements about the 8085. 1. It has a 16-bit data bus. 2. TRAP is a non-maskable interrupt. Which is/are correct?

    1. 1 only
    2. 2 only
    3. Both 1 and 2
    4. Neither 1 nor 2
    Answer

    B. 2 only

    The 8085 data bus is 8 bits.

39. Consider the statements. 1. SRAM needs periodic refresh. 2. DRAM stores bits on capacitors. Which is/are correct?

    1. 1 only
    2. 2 only
    3. Both 1 and 2
    4. Neither 1 nor 2
    Answer

    B. 2 only

    SRAM uses flip-flops and needs no refresh.

40. Consider the statements. 1. A ripple counter is a synchronous counter. 2. All flip-flops of a synchronous counter share a common clock. Which is/are correct?

    1. 1 only
    2. 2 only
    3. Both 1 and 2
    4. Neither 1 nor 2
    Answer

    B. 2 only

    Ripple counters are asynchronous; statement 1 is false.

41. Consider the statements about a full adder. 1. It has three inputs. 2. It can be built from two half adders and an OR gate. Which is/are correct?

    1. 1 only
    2. 2 only
    3. Both 1 and 2
    4. Neither 1 nor 2
    Answer

    C. Both 1 and 2

    Both are true.

42. Match the counter with its modulus (n flip-flops): P. Ripple counter Q. Ring counter R. Johnson counter 1. n 2. 2n 3. 2^n

    1. P-2, Q-3, R-1
    2. P-3, Q-2, R-1
    3. P-1, Q-2, R-3
    4. P-3, Q-1, R-2
    Answer

    D. P-3, Q-1, R-2

    Ripple 2^n, ring n, Johnson 2n.

43. Match the memory with its feature: P. EPROM Q. DRAM R. EEPROM 1. Needs refresh 2. UV erase 3. Electrical erase

    1. P-1, Q-2, R-3
    2. P-3, Q-1, R-2
    3. P-2, Q-3, R-1
    4. P-2, Q-1, R-3
    Answer

    D. P-2, Q-1, R-3

    EPROM by UV, DRAM refresh, EEPROM electrical.

44. Match the chip with its function: P. 8255 Q. 8259 R. 8237 1. DMA controller 2. Programmable peripheral interface 3. Interrupt controller

    1. P-3, Q-1, R-2
    2. P-2, Q-1, R-3
    3. P-2, Q-3, R-1
    4. P-1, Q-2, R-3
    Answer

    C. P-2, Q-3, R-1

    8255 PPI, 8259 interrupt controller, 8237 DMA controller.

45. Consider the statements. 1. Characteristic equation of a T flip-flop is Q⁺ = T ⊕ Q. 2. Characteristic equation of a D flip-flop is Q⁺ = D. Which is/are correct?

    1. 1 only
    2. 2 only
    3. Both 1 and 2
    4. Neither 1 nor 2
    Answer

    C. Both 1 and 2

    Both are standard.